Complex IC-chips (integrated circuit chips) are subjected to several tests as they are manufactured to both determine their functionality and to insure their future reliability. A “wafer” test is usually performed first. During this test, individual IC-chips in the wafer are probed. This is a quick test in which only certain types of defects in the IC-chips are detected. Thermal control during the wafer test is typically achieved simply with a cold plate that contacts the wafer.
The next test, which takes place after the IC-chips chips are packaged, is called “burn-in”. The burn-in test thermally and electrically stresses the IC-chips to accelerate “infant mortality” failures. The stressing causes immediate failures that otherwise would occur during the first 10% of the IC-chips' life in the field, thereby insuring a more reliable product for the customer. The burn-in test can take many hours to perform, and the temperature of the IC-chip typically is held in the 100° C. to 140° C. range. Because the IC-chips are also subjected to higher than normal voltages, the power dissipation in the IC-chip can be significantly higher than in normal operation. This extra power dissipation makes the task of controlling the temperature of the IC-chip very difficult. Further, in order to minimize the time required for burn-in, it is also desirable to keep the temperature of the IC-chip as high as possible without damaging the IC-chip.
A “class” test usually follows the burn-in test. Here, the IC-chips are speed sorted and the basic function of each IC-chip is verified. During this test, power dissipation in the IC-chip can vary wildly as the IC-chip is sent a stream of test signals. Because the operation of an IC-chip slows down as the temperature of the IC-chip increases, very tight temperature control of the IC-chip is required throughout the class test. This insures that the speed at which the IC-chip operates is measured precisely at a specified temperature. If the IC-chip temperature is too high, the operation of the IC-chip will get a slower speed rating. Then the IC-chip will be sold as a lower priced part.
In the prior art, the present inventors have already disclosed a system which will maintain the temperature of an IC-chip at a set-point as the IC-chip undergoes the above described “burn-in” test and “class” test. This prior art system is disclosed in U.S. Pat. No. 5,812,505 which is entitled “TEMPERATURE CONTROL SYSTEM FOR AN ELECTRONIC DEVICE WHICH ACHIEVES A QUICK RESPONSE BY INTERPOSING A HEATER BETWEEN THE DEVICE AND A HEAT SINK.” All of the details of that patent are herein incorporated by reference.
However, even though the system of patent '505 does in fact control the temperature of an IC-chip very accurately, the present inventors have now discovered one particular technical drawback with that system. This drawback has nothing to do with the accuracy at which the temperature of the IC-chip is maintained, and it is explained herein in the Detailed Description in conjunction with FIGS. 5–10.
Accordingly, the primary object of the present invention is to provide a novel temperature control system for an IC-chip which addresses and solves a technical drawback in system of patent '505.